Messages in this thread Patch in this message | | | From | Roger Lu <> | Subject | [PATCH v20 2/7] arm64: dts: mt8183: add svs device information | Date | Wed, 21 Jul 2021 15:08:59 +0800 |
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add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu <roger.lu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index f90df6439c08..1e57999a3add 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -743,6 +743,18 @@ status = "disabled"; }; + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + }; + thermal: thermal@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; @@ -1169,6 +1181,9 @@ mipi_tx_calibration: calib@190 { reg = <0x190 0xc>; }; + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; }; u3phy: t-phy@11f40000 { -- 2.18.0
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