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SubjectRe: [PATCH net-next V1 2/3] dt-bindings: net: imx-dwmac: convert imx-dwmac bindings to yaml
On Mon, Jul 19, 2021 at 03:18:20PM +0800, Joakim Zhang wrote:
> In order to automate the verification of DT nodes covert imx-dwmac to
> nxp,dwmac-imx.yaml, and pass below checking.
>
> $ make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
> $ make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> ---
> .../devicetree/bindings/net/imx-dwmac.txt | 56 -----------
> .../bindings/net/nxp,dwmac-imx.yaml | 93 +++++++++++++++++++
> 2 files changed, 93 insertions(+), 56 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/net/imx-dwmac.txt
> create mode 100644 Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/imx-dwmac.txt b/Documentation/devicetree/bindings/net/imx-dwmac.txt
> deleted file mode 100644
> index 921d522fe8d7..000000000000
> --- a/Documentation/devicetree/bindings/net/imx-dwmac.txt
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
> -
> -This file documents platform glue layer for IMX.
> -Please see stmmac.txt for the other unchanged properties.
> -
> -The device node has following properties.
> -
> -Required properties:
> -- compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
> - and "snps,dwmac-5.10a" to select IP version.
> -- clocks: Must contain a phandle for each entry in clock-names.
> -- clock-names: Should be "stmmaceth" for the host clock.
> - Should be "pclk" for the MAC apb clock.
> - Should be "ptp_ref" for the MAC timer clock.
> - Should be "tx" for the MAC RGMII TX clock:
> - Should be "mem" for EQOS MEM clock.
> - - "mem" clock is required for imx8dxl platform.
> - - "mem" clock is not required for imx8mp platform.
> -- interrupt-names: Should contain a list of interrupt names corresponding to
> - the interrupts in the interrupts property, if available.
> - Should be "macirq" for the main MAC IRQ
> - Should be "eth_wake_irq" for the IT which wake up system
> -- intf_mode: Should be phandle/offset pair. The phandle to the syscon node which
> - encompases the GPR register, and the offset of the GPR register.
> - - required for imx8mp platform.
> - - is optional for imx8dxl platform.
> -
> -Optional properties:
> -- intf_mode: is optional for imx8dxl platform.
> -- snps,rmii_refclk_ext: to select RMII reference clock from external.
> -
> -Example:
> - eqos: ethernet@30bf0000 {
> - compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
> - reg = <0x30bf0000 0x10000>;
> - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "eth_wake_irq", "macirq";
> - clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
> - <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
> - <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
> - <&clk IMX8MP_CLK_ENET_QOS>;
> - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
> - assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
> - <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
> - <&clk IMX8MP_CLK_ENET_QOS>;
> - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
> - <&clk IMX8MP_SYS_PLL2_100M>,
> - <&clk IMX8MP_SYS_PLL2_125M>;
> - assigned-clock-rates = <0>, <100000000>, <125000000>;
> - nvmem-cells = <&eth_mac0>;
> - nvmem-cell-names = "mac-address";
> - nvmem_macaddr_swap;
> - intf_mode = <&gpr 0x4>;
> - status = "disabled";
> - };
> diff --git a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
> new file mode 100644
> index 000000000000..5629b2e4ccf8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8 DWMAC glue layer Device Tree Bindings
> +
> +maintainers:
> + - Joakim Zhang <qiangqing.zhang@nxp.com>
> +
> +# We need a select here so we don't match all nodes with 'snps,dwmac'
> +select:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nxp,imx8mp-dwmac-eqos
> + - nxp,imx8dxl-dwmac-eqos
> + required:
> + - compatible
> +
> +allOf:
> + - $ref: "snps,dwmac.yaml#"
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:

Don't need 'oneOf' as there is only one entry.

> + - enum:
> + - nxp,imx8mp-dwmac-eqos
> + - nxp,imx8dxl-dwmac-eqos
> + - const: snps,dwmac-5.10a
> +
> + clocks:
> + minItems: 3
> + maxItems: 5
> + items:
> + - description: MAC host clock
> + - description: MAC apb clock
> + - description: MAC timer clock
> + - description: MAC RGMII TX clock
> + - description: EQOS MEM clock
> +
> + clock-names:
> + minItems: 3
> + maxItems: 5
> + contains:

s/contains/items/

But really, like the other one, can't you define the order?

> + enum:
> + - stmmaceth
> + - pclk
> + - ptp_ref
> + - tx
> + - mem
> +
> + intf_mode:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Should be phandle/offset pair. The phandle to the syscon node which
> + encompases the GPR register, and the offset of the GPR register.

Sounds like 2 cells:

maxItems: 2

> +
> + snps,rmii_refclk_ext:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + To select RMII reference clock from external.
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/imx8mp-clock.h>
> +
> + eqos: ethernet@30bf0000 {
> + compatible = "nxp,imx8mp-dwmac-eqos","snps,dwmac-5.10a";
> + reg = <0x30bf0000 0x10000>;
> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_wake_irq";
> + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
> + <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
> + <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
> + <&clk IMX8MP_CLK_ENET_QOS>;
> + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
> + phy-mode = "rgmii";
> + status = "disabled";

Why are you disabling your example? Drop.

> + };
> --
> 2.17.1
>
>

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