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SubjectRe: [PATCH 2/2] clk: at91: add register definition for sama7g5's master clock
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On 19/07/2021 at 10:03, Claudiu Beznea wrote:
> Add register definitions for SAMA7G5's master clock. These would be
> also used by architecture specific power saving code.
>
> Fixes: 6cb0e54412a3 ("ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
>
> Hi Stephen,
>
> This is a part from patch at [1]. I keep it at minimum (only definitions)
> for faster acceptance as the build is broken on arm multi_v7_defconfig
> without it).
> In next version of patch at [1] I will update it accordingly.

Stephen,

Before hearing from you I inserted this patch in our at91-soc branch
that is part of linux-next. With this at least the build don't break
anymore.

Tell me if you want to have an immutable branch that we could share with
it on top of 5.14-rc1 or if it's fine if we add the same patch in both
of our trees.

Best regards,
Nicolas


> [1] https://lore.kernel.org/linux-clk/20210401122726.28528-5-claudiu.beznea@microchip.com/
>
> include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
> index a4f82e836a7c..ccb3f034bfa9 100644
> --- a/include/linux/clk/at91_pmc.h
> +++ b/include/linux/clk/at91_pmc.h
> @@ -137,6 +137,32 @@
> #define AT91_PMC_PLLADIV2_ON (1 << 12)
> #define AT91_PMC_H32MXDIV BIT(24)
>
> +#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
> +#define AT91_PMC_MCR_V2_ID_MSK (0xF)
> +#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK)
> +#define AT91_PMC_MCR_V2_CMD (1 << 7)
> +#define AT91_PMC_MCR_V2_DIV (7 << 8)
> +#define AT91_PMC_MCR_V2_DIV1 (0 << 8)
> +#define AT91_PMC_MCR_V2_DIV2 (1 << 8)
> +#define AT91_PMC_MCR_V2_DIV4 (2 << 8)
> +#define AT91_PMC_MCR_V2_DIV8 (3 << 8)
> +#define AT91_PMC_MCR_V2_DIV16 (4 << 8)
> +#define AT91_PMC_MCR_V2_DIV32 (5 << 8)
> +#define AT91_PMC_MCR_V2_DIV64 (6 << 8)
> +#define AT91_PMC_MCR_V2_DIV3 (7 << 8)
> +#define AT91_PMC_MCR_V2_CSS (0x1F << 16)
> +#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16)
> +#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16)
> +#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16)
> +#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16)
> +#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16)
> +#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16)
> +#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16)
> +#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16)
> +#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16)
> +#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16)
> +#define AT91_PMC_MCR_V2_EN (1 << 28)
> +
> #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
>
> #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
>


--
Nicolas Ferre

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