Messages in this thread Patch in this message | | | From | Andy Shevchenko <> | Subject | [PATCH v2 2/3] clk: fractional-divider: Introduce NO_PRESCALER flag | Date | Fri, 16 Jul 2021 16:34:47 +0300 |
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The newly introduced flag, when set, makes the flow to skip the assumption that the caller will use an additional 2^scale prescaler to get the desired clock rate.
Reported-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- v2: moved entire snipped under new flag check (Liu) drivers/clk/clk-fractional-divider.c | 10 ++++++---- include/linux/clk-provider.h | 5 +++++ 2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 535d299af646..5f4b6a8aef67 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -76,16 +76,18 @@ void clk_fractional_divider_general_approximation(struct clk_hw *hw, unsigned long *m, unsigned long *n) { struct clk_fractional_divider *fd = to_clk_fd(hw); - unsigned long scale; /* * Get rate closer to *parent_rate to guarantee there is no overflow * for m and n. In the result it will be the nearest rate left shifted * by (scale - fd->nwidth) bits. */ - scale = fls_long(*parent_rate / rate - 1); - if (scale > fd->nwidth) - rate <<= scale - fd->nwidth; + if (!(fd->flags & CLK_FRAC_DIVIDER_NO_PRESCALER)) { + unsigned long scale = fls_long(*parent_rate / rate - 1); + + if (scale > fd->nwidth) + rate <<= scale - fd->nwidth; + } rational_best_approximation(rate, *parent_rate, GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index d83b829305c0..f74d0afe275f 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1001,6 +1001,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are * used for the divider register. Setting this flag makes the register * accesses big endian. + * CLK_FRAC_DIVIDER_NO_PRESCALER - By default the resulting rate may be shifted + * left by a few bits in case when the asked one is quite small to satisfy + * the desired range of denominator. If the caller wants to get the best + * rate without using an additional prescaler, this flag may be set. */ struct clk_fractional_divider { struct clk_hw hw; @@ -1022,6 +1026,7 @@ struct clk_fractional_divider { #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) +#define CLK_FRAC_DIVIDER_NO_PRESCALER BIT(2) extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, -- 2.30.2
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