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    Subject[PATCH 5.13 086/266] drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7
    Date
    From: Wesley Chalmers <Wesley.Chalmers@amd.com>

    [ Upstream commit 3577e1678772ce3ede92af3a75b44a4b76f9b4ad ]

    [WHY]
    DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when
    changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back.

    Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
    Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
    Acked-by: Stylon Wang <stylon.wang@amd.com>
    Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
    index 6a10daec15cc..793554e61c52 100644
    --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
    +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
    @@ -243,7 +243,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
    REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);

    /* This value is dependent on the hardware pipeline delay so set once per SOC */
    - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
    + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
    }

    void dcn20_disable_vga(
    --
    2.30.2


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