Messages in this thread Patch in this message | | | From | Greg Kroah-Hartman <> | Subject | [PATCH 5.12 225/242] media: ccs: Fix the op_pll_multiplier address | Date | Thu, 15 Jul 2021 20:39:47 +0200 |
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From: Bernhard Wimmer <be.wimm@gmail.com>
commit 0e3e0c9369c822b7f1dd11504eeb98cfd4aabf24 upstream.
According to the CCS spec the op_pll_multiplier address is 0x030e, not 0x031e.
Signed-off-by: Bernhard Wimmer <be.wimm@gmail.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Cc: stable@vger.kernel.org Fixes: 6493c4b777c2 ("media: smiapp: Import CCS definitions") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> --- drivers/media/i2c/ccs/ccs-limits.c | 4 ++++ drivers/media/i2c/ccs/ccs-limits.h | 4 ++++ drivers/media/i2c/ccs/ccs-regs.h | 6 +++++- 3 files changed, 13 insertions(+), 1 deletion(-)
--- a/drivers/media/i2c/ccs/ccs-limits.c +++ b/drivers/media/i2c/ccs/ccs-limits.c @@ -1,5 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause /* Copyright (C) 2019--2020 Intel Corporation */ +/* + * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs; + * do not modify. + */ #include "ccs-limits.h" #include "ccs-regs.h" --- a/drivers/media/i2c/ccs/ccs-limits.h +++ b/drivers/media/i2c/ccs/ccs-limits.h @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ /* Copyright (C) 2019--2020 Intel Corporation */ +/* + * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs; + * do not modify. + */ #ifndef __CCS_LIMITS_H__ #define __CCS_LIMITS_H__ --- a/drivers/media/i2c/ccs/ccs-regs.h +++ b/drivers/media/i2c/ccs/ccs-regs.h @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ /* Copyright (C) 2019--2020 Intel Corporation */ +/* + * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs; + * do not modify. + */ #ifndef __CCS_REGS_H__ #define __CCS_REGS_H__ @@ -202,7 +206,7 @@ #define CCS_R_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT) #define CCS_R_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT) #define CCS_R_OP_PRE_PLL_CLK_DIV (0x030c | CCS_FL_16BIT) -#define CCS_R_OP_PLL_MULTIPLIER (0x031e | CCS_FL_16BIT) +#define CCS_R_OP_PLL_MULTIPLIER (0x030e | CCS_FL_16BIT) #define CCS_R_PLL_MODE 0x0310 #define CCS_PLL_MODE_SHIFT 0U #define CCS_PLL_MODE_MASK 0x1
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