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    Subject[PATCH 5.12 035/242] clk: renesas: r8a77995: Add ZA2 clock
    Date
    From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

    [ Upstream commit 790c06cc5df263cdaff748670cc65958c81b0951 ]

    R-Car D3 ZA2 clock is from PLL0D3 or S0,
    and it can be controlled by ZA2CKCR.
    It is needed for R-Car Sound, but is not used so far.
    Using default settings is very enough at this point.
    This patch adds it by DEF_FIXED().

    Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
    Link: https://lore.kernel.org/r/87pmxclrmy.wl-kuninori.morimoto.gx@renesas.com
    Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
    index 9cfd00cf4e69..81c0bc1e78af 100644
    --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
    +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
    @@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
    DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),

    /* Core Clock Outputs */
    + DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
    DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
    DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
    DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
    --
    2.30.2


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