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SubjectRe: [PATCH v2 5/5] mailbox: cmdq: fix GCE can not receive hardward event
On Mon, Jul 5, 2021 at 1:35 PM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> For the design of GCE hardware event signal transportation,
> evnet rx will send the event signal to all GCE event merges
> after receiving the event signal from the other hardware.
>
> Because GCE event merges need to response to event rx, their
> clocks must be enabled at that time.
>
> To make sure all the gce clock is enabled while receiving the
> hardware event, each cmdq mailbox should enable or disable
> the others gce clk at the same time.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 102 +++++++++++++++++++++++------
> 1 file changed, 83 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index fc67888a677c..44a3cf252fd5 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -19,6 +19,7 @@
>
> #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
> #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
> +#define CMDQ_GCE_NUM_MAX (2)
>
> #define CMDQ_CURR_IRQ_STATUS 0x10
> #define CMDQ_SYNC_TOKEN_UPDATE 0x68
> @@ -73,14 +74,16 @@ struct cmdq {
> u32 thread_nr;
> u32 irq_mask;
> struct cmdq_thread *thread;
> - struct clk *clock;
> + struct clk *clock[CMDQ_GCE_NUM_MAX];
> bool suspended;
> u8 shift_pa;
> + u32 gce_num;
> };
>
> struct gce_plat {
> u32 thread_nr;
> u8 shift;
> + u32 gce_num;
> };
>
> u8 cmdq_get_shift_pa(struct mbox_chan *chan)
> @@ -120,11 +123,15 @@ static void cmdq_init(struct cmdq *cmdq)
> {
> int i;
>
> - WARN_ON(clk_enable(cmdq->clock) < 0);
> + for (i = 0; i < cmdq->gce_num; i++)
> + WARN_ON(clk_enable(cmdq->clock[i]) < 0);
> +
You can use clk_bulk_enable instead of looping. Same for clk_bulk_disable.

<snip>

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