Messages in this thread | | | Date | Mon, 12 Jul 2021 15:44:11 +0100 | From | "Russell King (Oracle)" <> | Subject | Re: [PATCH v4 11/11] perf auxtrace: Add compat_auxtrace_mmap__{read_head|write_tail} |
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On Sun, Jul 11, 2021 at 06:41:05PM +0800, Leo Yan wrote: > When perf runs in compat mode (kernel in 64-bit mode and the perf is in > 32-bit mode), the 64-bit value atomicity in the user space cannot be > assured, E.g. on some architectures, the 64-bit value accessing is split > into two instructions, one is for the low 32-bit word accessing and > another is for the high 32-bit word.
Does this apply to 32-bit ARM code on aarch64? I would not have thought it would, as the structure member is a __u64 and compat_auxtrace_mmap__read_head() doesn't seem to be marking anything as packed, so the compiler _should_ be able to use a LDRD instruction to load the value.
Is this a problem noticed on non-ARM architectures?
Thanks.
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