Messages in this thread | | | Date | Mon, 12 Jul 2021 19:36:46 +0800 | From | Leo Yan <> | Subject | Re: [PATCH v2] coresight: tmc-etr: Speed up for bounce buffer in flat mode |
| |
On Mon, Jul 12, 2021 at 12:17:04PM +0100, Suzuki Kuruppassery Poulose wrote:
[...]
> > I am doubt why you conclude "always start tracing at the beginning of > > the buffer"? I read the driver but cannot find any code in the driver > > to reset rrp and rwp after fetching the trace data, or there have any > > implict operation to reset pointers? > > The ETR is always programmed with the base address of the "ETR" buffer, > which is *not the same* as the perf ring buffer, since we always do > double buffering. We do not program the RRP/RWP of the ETR (except > for the SoC-600, where it is mandatory and we set them to the base > address). Thus there is no context associated with the ETR buffer. > But at the end of the run, we do read the RRP/ RWP to figure out > where the ETR has reached. > > As for reseting the RRP / RWP, at the beginning of a session, is > done implicitly for the ETR (except for SoC-600 ETRs as explained > above) by the hardware to the base address.
Yes, I finally matched your description with the code. Will respin patch for this.
Thanks for confirmation! Leo
| |