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    Subject[PATCH 5.12 108/700] perf/x86/intel: Fix instructions:ppp support in Sapphire Rapids
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    commit 1d5c7880992a06679585e7e568cc679c0c5fd4f2 upstream.

    Perf errors out when sampling instructions:ppp.

    $ perf record -e instructions:ppp -- true
    Error:
    The sys_perf_event_open() syscall returned with 22 (Invalid argument)
    for event (instructions:ppp).

    The instruction PDIR is only available on the fixed counter 0. The event
    constraint has been updated to fixed0_constraint in
    icl_get_event_constraints(). The Sapphire Rapids codes unconditionally
    error out for the event which is not available on the GP counter 0.

    Make the instructions:ppp an exception.

    Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
    Reported-by: Yasin, Ahmad <ahmad.yasin@intel.com>
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: stable@vger.kernel.org
    Link: https://lore.kernel.org/r/1624029174-122219-4-git-send-email-kan.liang@linux.intel.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/events/intel/core.c | 4 +++-
    1 file changed, 3 insertions(+), 1 deletion(-)

    --- a/arch/x86/events/intel/core.c
    +++ b/arch/x86/events/intel/core.c
    @@ -3975,8 +3975,10 @@ spr_get_event_constraints(struct cpu_hw_
    * The :ppp indicates the Precise Distribution (PDist) facility, which
    * is only supported on the GP counter 0. If a :ppp event which is not
    * available on the GP counter 0, error out.
    + * Exception: Instruction PDIR is only available on the fixed counter 0.
    */
    - if (event->attr.precise_ip == 3) {
    + if ((event->attr.precise_ip == 3) &&
    + !constraint_match(&fixed0_constraint, event->hw.config)) {
    if (c->idxmsk64 & BIT_ULL(0))
    return &counter0_constraint;


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