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    Subject[PATCH 5.12 107/700] perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    commit d18216fafecf2a3a7c2b97086892269d6ab3cd5e upstream.

    On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which
    rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the
    count value is not correct.

    Update intel_spr_extra_regs[] to support them.

    Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: stable@vger.kernel.org
    Link: https://lore.kernel.org/r/1624029174-122219-3-git-send-email-kan.liang@linux.intel.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/events/intel/core.c | 2 ++
    1 file changed, 2 insertions(+)

    --- a/arch/x86/events/intel/core.c
    +++ b/arch/x86/events/intel/core.c
    @@ -280,6 +280,8 @@ static struct extra_reg intel_spr_extra_
    INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
    INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
    INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
    + INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
    + INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
    EVENT_EXTRA_END
    };


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