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    Subject[PATCH v1 01/13] ARM: tegra: Add SoC thermal sensor to Tegra30 device-trees
    Date
    Add the on-chip SoC thermal sensor to Tegra30 device-trees. Now CPU
    temperature reporting and thermal throttling is available on all Tegra30
    devices universally.

    Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
    ---
    arch/arm/boot/dts/tegra30.dtsi | 87 ++++++++++++++++++++++++++++++++--
    1 file changed, 83 insertions(+), 4 deletions(-)

    diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
    index c577c191be4b..eaf4951d9ff8 100644
    --- a/arch/arm/boot/dts/tegra30.dtsi
    +++ b/arch/arm/boot/dts/tegra30.dtsi
    @@ -5,6 +5,7 @@
    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/soc/tegra-pmc.h>
    +#include <dt-bindings/thermal/thermal.h>

    #include "tegra30-peripherals-opp.dtsi"

    @@ -800,6 +801,20 @@ fuse@7000f800 {
    reset-names = "fuse";
    };

    + tsensor: tsensor@70014000 {
    + compatible = "nvidia,tegra30-tsensor";
    + reg = <0x70014000 0x500>;
    + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
    + resets = <&tegra_car TEGRA30_CLK_TSENSOR>;
    +
    + assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
    + assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
    + assigned-clock-rates = <500000>;
    +
    + #thermal-sensor-cells = <1>;
    + };
    +
    hda@70030000 {
    compatible = "nvidia,tegra30-hda";
    reg = <0x70030000 0x10000>;
    @@ -1062,32 +1077,36 @@ cpus {
    #address-cells = <1>;
    #size-cells = <0>;

    - cpu@0 {
    + cpu0: cpu@0 {
    device_type = "cpu";
    compatible = "arm,cortex-a9";
    reg = <0>;
    clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
    + #cooling-cells = <2>;
    };

    - cpu@1 {
    + cpu1: cpu@1 {
    device_type = "cpu";
    compatible = "arm,cortex-a9";
    reg = <1>;
    clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
    + #cooling-cells = <2>;
    };

    - cpu@2 {
    + cpu2: cpu@2 {
    device_type = "cpu";
    compatible = "arm,cortex-a9";
    reg = <2>;
    clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
    + #cooling-cells = <2>;
    };

    - cpu@3 {
    + cpu3: cpu@3 {
    device_type = "cpu";
    compatible = "arm,cortex-a9";
    reg = <3>;
    clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
    + #cooling-cells = <2>;
    };
    };

    @@ -1102,4 +1121,64 @@ pmu {
    <&{/cpus/cpu@2}>,
    <&{/cpus/cpu@3}>;
    };
    +
    + thermal-zones {
    + tsensor0-thermal {
    + polling-delay-passive = <1000>; /* milliseconds */
    + polling-delay = <5000>; /* milliseconds */
    +
    + thermal-sensors = <&tsensor 0>;
    +
    + trips {
    + level1_trip: dvfs-alert {
    + /* throttle at 80C until temperature drops to 79.8C */
    + temperature = <80000>;
    + hysteresis = <200>;
    + type = "passive";
    + };
    +
    + level2_trip: cpu-div2-throttle {
    + /* hardware CPU x2 freq throttle at 85C */
    + temperature = <85000>;
    + hysteresis = <200>;
    + type = "hot";
    + };
    +
    + level3_trip: soc-critical {
    + /* hardware shut down at 90C */
    + temperature = <90000>;
    + hysteresis = <2000>;
    + type = "critical";
    + };
    + };
    +
    + cooling-maps {
    + map0 {
    + trip = <&level1_trip>;
    + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    + <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
    + };
    + };
    + };
    +
    + tsensor1-thermal {
    + status = "disabled";
    +
    + polling-delay-passive = <1000>; /* milliseconds */
    + polling-delay = <0>; /* milliseconds */
    +
    + thermal-sensors = <&tsensor 1>;
    +
    + trips {
    + dvfs-alert {
    + temperature = <80000>;
    + hysteresis = <200>;
    + type = "passive";
    + };
    + };
    + };
    + };
    };
    --
    2.32.0
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