Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Wed, 9 Jun 2021 17:57:43 +0200 | Subject | Re: [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's |
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Hi Prabhakar,
On Wed, Jun 9, 2021 at 5:50 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Wed, Jun 9, 2021 at 8:27 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > Add support for reading the LSI DEVID register which is present in > > > SYSC block of RZ/G2{L,LC} SoC's. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- a/drivers/soc/renesas/renesas-soc.c > > > +++ b/drivers/soc/renesas/renesas-soc.c > > > @@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = { > > > .reg = 0xfff00044, /* PRR (Product Register) */ > > > }; > > > > > > +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = { > > > + .name = "RZ/G2L", > > > + .reg = 0x11020a04, > > > > Please don't add hardcoded register addresses for new SoCs (i.e. drop > > ".reg"). The "renesas,r9a07g044-sysc" is always present. > > And if it were missing, the hardcoded fallback would lead into the > > classic CCCR/PRR scheme, which is not correct for RZ/G2L... > > > I wanted to avoid iomap for the entire sysc block for just a single register.
The mapping will be rounded up to PAGE_SIZE anyway (I know, SYSC is 64 KiB, hence larger than the typical page size).
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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