Messages in this thread | | | Date | Tue, 8 Jun 2021 17:32:03 +0200 | From | 'Christoph Hellwig' <> | Subject | Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support |
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On Tue, Jun 08, 2021 at 03:00:17PM +0000, David Laight wrote: > It is almost impossible to interface to many ethernet chips without > either coherent or uncached memory for the descriptor rings. > The status bits on the transmit ring are particularly problematic. > > The receive ring can be done with writeback+invalidate provided you > fill a cache line at a time.
It is horrible, but it has been done. Take a look at:
drivers/net/ethernet/i825xx/lasi_82596.c and drivers/net/ethernet/seeq/sgiseeq.c
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