Messages in this thread | | | From | Dan Williams <> | Date | Sat, 5 Jun 2021 17:30:30 -0700 | Subject | Re: [PATCH V3.1] cxl/mem: Map registers based on capabilities |
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On Thu, Jun 3, 2021 at 5:51 PM <ira.weiny@intel.com> wrote: > > From: Ira Weiny <ira.weiny@intel.com> > > The information required to map registers based on capabilities is > contained within the bars themselves. This means the bar must be mapped > to read the information needed and then unmapped to map the individual > parts of the BAR based on capabilities. > > Change cxl_setup_device_regs() to return a new cxl_register_map, change > the name to cxl_probe_device_regs(). Allocate and place > cxl_register_maps on a list while processing all of the specified > register blocks. > > After probing all the register blocks go back and map smaller registers > blocks based on their capabilities and dispose of the cxl_register_maps. > > NOTE: pci_iomap() is not managed automatically via pcim_enable_device() > so be careful to call pci_iounmap() correctly. > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Signed-off-by: Ira Weiny <ira.weiny@intel.com> > Link: https://lore.kernel.org/r/20210528004922.3980613-4-ira.weiny@intel.com > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > > --- > Changes for V3.1 > Fix 0-day > > >> drivers/cxl/core.c:40:17: warning: variable 'register_block' set but not used [-Wunused-but-set-variable] > 40 | void __iomem *register_block;
Just a note for next time if you want to be friendly to "b4 am" using maintainers. Roll the version and include the patch number in the resend, i.e.: in this case: "[PATCH v4 3/5] cxl/mem: Map registers based on capabilities". I was able to manually create a bundle in the proper order on patchwork for the two "3.1" updates.
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