| From | kan.liang@linux ... | Subject | [PATCH V4 06/16] perf/x86/intel/uncore: Add Sapphire Rapids server PCU support | Date | Wed, 30 Jun 2021 14:08:30 -0700 |
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From: Kan Liang <kan.liang@linux.intel.com>
The PCU is the primary power controller for the Sapphire Rapids.
Except the name, all the information can be retrieved from the discovery tables.
Reviewed-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- arch/x86/events/intel/uncore_snbep.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index b1bc82c..006d111 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5475,6 +5475,10 @@ static struct intel_uncore_type spr_uncore_m2pcie = { .name = "m2pcie", }; +static struct intel_uncore_type spr_uncore_pcu = { + .name = "pcu", +}; + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { @@ -5482,7 +5486,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { &spr_uncore_iio, &spr_uncore_irp, &spr_uncore_m2pcie, - NULL, + &spr_uncore_pcu, NULL, NULL, NULL, -- 2.7.4
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