Messages in this thread | | | Subject | Re: [PATCH v3 3/3] clk: meson: regmap: switch to determine_rate for the dividers | From | Stephen Boyd <> | Date | Wed, 30 Jun 2021 11:39:20 -0700 |
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Quoting Martin Blumenstingl (2021-06-27 15:39:59) > This increases the maxmium supported frequency on 32-bit systems from > 2^31 (signed long as used by clk_ops.round_rate, maximum value: > approx. 2.14GHz) to 2^32 (unsigned long as used by > clk_ops.determine_rate, maximum value: approx. 4.29GHz). > On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are > capable of running at up to 2.97GHz. So switch the divider > implementation in clk-regmap to clk_ops.determine_rate to support these > higher frequencies on 32-bit systems. > > Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > ---
Applied to clk-next
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