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SubjectRe: [PATCH 50/54] KVM: x86/mmu: Optimize and clean up so called "last nonleaf level" logic
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On 22/06/21 19:57, Sean Christopherson wrote:
> For 32-bit paging (non-PAE), the adjustments are needed purely because
> bit 7 is ignored if PSE=0. Retain that logic as is, but make
> is_last_gpte() unique per PTTYPE

... which makes total sense given where it's used, too.

> +#if PTTYPE == 32
> + /*
> + * 32-bit paging requires special handling because bit 7 is ignored if
> + * CR4.PSE=0, not reserved. Clear bit 7 in the gpte if the level is
> + * greater than the last level for which bit 7 is the PAGE_SIZE bit.
> + *
> + * The RHS has bit 7 set iff level < (2 + PSE). If it is clear, bit 7
> + * is not reserved and does not indicate a large page at this level,
> + * so clear PT_PAGE_SIZE_MASK in gpte if that is the case.
> + */
> + gpte &= level - (PT32_ROOT_LEVEL + !!mmu->mmu_role.ext.cr4_pse);

!! is not needed and possibly slightly confusing? (We know it's a
single bit).

Paolo

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