Messages in this thread | | | From | David Laight <> | Subject | RE: [PATCH] firmware: export x86_64 platform flash bios region via sysfs | Date | Wed, 23 Jun 2021 13:22:51 +0000 |
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From: Hans-Gert Dahmen > Sent: 23 June 2021 13:18 > > these are some good points. > > On 23.06.21 00:18, David Laight wrote: > > Are you saying that my 15 year old 64bit Athlon cpu and bios > > have this large SPI flash > > No. The reads will wrap, i.e. if your flash is 2MB then it would be > repeated 8 times in the 16MB window. > > > and the required hardware to > > convert bus cycles to serial spi reads? > > Yes. The window is part of the DMI interface and the south bridge or PCH > converts the bus cycles to SPI reads. It is because this region contains > the reset vector address of your CPU and the very first instruction it > executes after a reset when the internal setup is done will actually be > loaded from the serial SPI bus. It is AFAIK part of AMD's original > 64-bit specification. > > However, after reading your mail I understand that I should have looked > up the exact explanations in the respective specs. So to definitively > answer your question I need to know which south bridge there is in your > 15 year old system and have a look into its datasheet. Do you know which > one it is by any chance?
Absolutely no idea. That particular system doesn't actually boot any more with either cpu I have for it plugged it. I suspect the psu voltages are out of range and have broken it.
But that isn't the point.
David
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