Messages in this thread | | | From | Heiko Stübner <> | Subject | Re: [PATCH 09/10] arm64: dts: rockchip: add pwm nodes for rk3568 | Date | Tue, 22 Jun 2021 12:36:59 +0200 |
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Am Dienstag, 22. Juni 2021, 12:29:06 CEST schrieb Heiko Stuebner: > From: Liang Chen <cl@rock-chips.com> > > Add the pwm controller nodes to the core rk3568 dtsi. > > Signed-off-by: Liang Chen <cl@rock-chips.com> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
please ignore the numbering, as they should be 09/10 -> 1/2 10/10 -> 2/2
> --- > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 176 +++++++++++++++++++++++ > 1 file changed, 176 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > index d225e6a45d5c..33db226b46cb 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -257,6 +257,50 @@ uart0: serial@fdd50000 { > status = "disabled"; > }; > > + pwm0: pwm@fdd70000 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfdd70000 0x0 0x10>; > + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm0m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm1: pwm@fdd70010 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfdd70010 0x0 0x10>; > + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm1m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm2: pwm@fdd70020 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfdd70020 0x0 0x10>; > + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm2m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm3: pwm@fdd70030 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfdd70030 0x0 0x10>; > + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm3_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > sdmmc2: mmc@fe000000 { > compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; > reg = <0x0 0xfe000000 0x0 0x4000>; > @@ -525,6 +569,138 @@ uart9: serial@fe6d0000 { > status = "disabled"; > }; > > + pwm4: pwm@fe6e0000 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6e0000 0x0 0x10>; > + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm4_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm5: pwm@fe6e0010 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6e0010 0x0 0x10>; > + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm5_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm6: pwm@fe6e0020 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6e0020 0x0 0x10>; > + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm6_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm7: pwm@fe6e0030 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6e0030 0x0 0x10>; > + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm7_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm8: pwm@fe6f0000 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6f0000 0x0 0x10>; > + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm8m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm9: pwm@fe6f0010 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6f0010 0x0 0x10>; > + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm9m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm10: pwm@fe6f0020 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6f0020 0x0 0x10>; > + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm10m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm11: pwm@fe6f0030 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe6f0030 0x0 0x10>; > + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm11m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm12: pwm@fe700000 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe700000 0x0 0x10>; > + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm12m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm13: pwm@fe700010 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe700010 0x0 0x10>; > + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm13m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm14: pwm@fe700020 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe700020 0x0 0x10>; > + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm14m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm15: pwm@fe700030 { > + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfe700030 0x0 0x10>; > + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm15m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > pinctrl: pinctrl { > compatible = "rockchip,rk3568-pinctrl"; > rockchip,grf = <&grf>; >
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