Messages in this thread | | | Subject | Re: [PATCH v3] KVM: LAPIC: Keep stored TMCCT register value 0 after KVM_SET_LAPIC | From | Paolo Bonzini <> | Date | Thu, 17 Jun 2021 20:26:15 +0200 |
| |
On 09/06/21 09:16, Wanpeng Li wrote: > From: Wanpeng Li <wanpengli@tencent.com> > > KVM_GET_LAPIC stores the current value of TMCCT and KVM_SET_LAPIC's memcpy > stores it in vcpu->arch.apic->regs, KVM_SET_LAPIC could store zero in > vcpu->arch.apic->regs after it uses it, and then the stored value would > always be zero. In addition, the TMCCT is always computed on-demand and > never directly readable. > > Suggested-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > --- > arch/x86/kvm/lapic.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 6d72d8f43310..9bd29b3ca790 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2628,6 +2628,7 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) > apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); > update_divide_count(apic); > __start_apic_timer(apic, APIC_TMCCT); > + kvm_lapic_set_reg(apic, APIC_TMCCT, 0); > kvm_apic_update_apicv(vcpu); > apic->highest_isr_cache = -1; > if (vcpu->arch.apicv_active) { >
Queued, thanks.
Paolo
| |