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SubjectRe: [PATCH v4 1/3] dt-bindings: msm: dsi: add missing 7nm bindings
On Thu, Jun 17, 2021 at 8:09 AM Jonathan Marek <jonathan@marek.ca> wrote:
>
> These got lost when going from .txt to .yaml bindings, add them back.
>

Fixes: 8fc939e72ff8 ("dt-bindings: msm: dsi: add yaml schemas for DSI
PHY bindings")

> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../bindings/display/msm/dsi-phy-7nm.yaml | 66 +++++++++++++++++++
> 1 file changed, 66 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
> new file mode 100644
> index 000000000000..c0077ca7e9e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DSI 7nm PHY
> +
> +maintainers:
> + - Jonathan Marek <jonathan@marek.ca>
> +
> +allOf:
> + - $ref: dsi-phy-common.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: qcom,dsi-phy-7nm
> + - const: qcom,dsi-phy-7nm-8150
> +
> + reg:
> + items:
> + - description: dsi phy register set
> + - description: dsi phy lane register set
> + - description: dsi pll register set
> +
> + reg-names:
> + items:
> + - const: dsi_phy
> + - const: dsi_phy_lane
> + - const: dsi_pll
> +
> + vdds-supply:
> + description: |
> + Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - vdds-supply
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + dsi-phy@ae94400 {
> + compatible = "qcom,dsi-phy-7nm";
> + reg = <0x0ae94400 0x200>,
> + <0x0ae94600 0x280>,
> + <0x0ae94900 0x260>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + vdds-supply = <&vreg_l5a_0p88>;
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> + };
> --
> 2.26.1
>

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