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Subject[PATCH v5 2/8] gpio: regmap: Add quirk for aliased data registers
Date
Some chips have the read-only input and write-only output data registers
aliased to the same offset. As a result it is not possible to perform
read-modify-writes on the output values, when a line is still configured
as input.

Add a quirk for aliased data registers, and document how the regmap
should be set up for correct operation.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
drivers/gpio/gpio-regmap.c | 7 ++++++-
include/linux/gpio/regmap.h | 13 +++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
index 134cedf151a7..3a3d0d9a945c 100644
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -15,6 +15,7 @@ struct gpio_regmap {
struct device *parent;
struct regmap *regmap;
struct gpio_chip gpio_chip;
+ unsigned int quirks;

int reg_stride;
int ngpio_per_reg;
@@ -68,7 +69,10 @@ static int gpio_regmap_get(struct gpio_chip *chip, unsigned int offset)
if (ret)
return ret;

- ret = regmap_read(gpio->regmap, reg, &val);
+ if (gpio->quirks & GPIO_REGMAP_QUIRK_ALIASED_DATA)
+ ret = regmap_read_bypassed(gpio->regmap, reg, &val);
+ else
+ ret = regmap_read(gpio->regmap, reg, &val);
if (ret)
return ret;

@@ -227,6 +231,7 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config

gpio->parent = config->parent;
gpio->regmap = config->regmap;
+ gpio->quirks = config->quirks;
gpio->ngpio_per_reg = config->ngpio_per_reg;
gpio->reg_stride = config->reg_stride;
gpio->reg_mask_xlate = config->reg_mask_xlate;
diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
index 334dd928042b..b0751a10fa4a 100644
--- a/include/linux/gpio/regmap.h
+++ b/include/linux/gpio/regmap.h
@@ -12,6 +12,17 @@ struct regmap;
#define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1))
#define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO)

+enum gpio_regmap_quirk {
+ /*
+ * For hardware where the (read-only) input and (write-only) output
+ * registers are aliased to the same offset. In this case the register
+ * must not be marked as volatile and a regcache must be used, to cache
+ * the write-only output values. Register reads for the input values
+ * will be performed by bypassing the cache.
+ */
+ GPIO_REGMAP_QUIRK_ALIASED_DATA = BIT(0),
+};
+
/**
* struct gpio_regmap_config - Description of a generic regmap gpio_chip.
* @parent: The parent device
@@ -31,6 +42,7 @@ struct regmap;
* @reg_stride: (Optional) May be set if the registers (of the
* same type, dat, set, etc) are not consecutive.
* @ngpio_per_reg: Number of GPIOs per register
+ * @quirks: Flags indicating GPIO chip hardware issues
* @irq_domain: (Optional) IRQ domain if the controller is
* interrupt-capable
* @reg_mask_xlate: (Optional) Translates base address and GPIO
@@ -73,6 +85,7 @@ struct gpio_regmap_config {
unsigned int reg_dir_out_base;
int reg_stride;
int ngpio_per_reg;
+ unsigned int quirks;
struct irq_domain *irq_domain;

int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
--
2.31.1
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