Messages in this thread | | | Date | Fri, 11 Jun 2021 14:31:29 -0700 | From | Pawan Gupta <> | Subject | Re: [PATCH 1/4] x86/msr: Define new bits in TSX_FORCE_ABORT MSR |
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On 11.06.2021 10:39, Borislav Petkov wrote: >On Wed, Jun 09, 2021 at 01:58:02PM -0700, Pawan Gupta wrote: >> Intel client processors that support IA32_TSX_FORCE_ABORT MSR related to >> perf counter interaction [1] received a microcode update that deprecates >> Transactional Synchronization Extension (TSX) feature. MSR >> IA32_TSX_FORCE_ABORT bit FORCE_ABORT_RTM now defaults to 1, writes to >> this bit are ignored. A new bit TSX_CPUID_CLEAR clears the TSX related >> CPUID bits. >> >> Below is the summary of changes to IA32_TSX_FORCE_ABORT MSR: >> >> Bit 0: FORCE_ABORT_RTM (legacy bit, new default=1) Status bit that >> indicates if RTM transactions are always aborted. This bit is >> essentially !SDV_ENABLE_RTM(Bit 2). Writes to this bit are ignored. >> >> Bit 1: TSX_CPUID_CLEAR (new bit, default=0) When set, CPUID.HLE = 0 >> and CPUID.RTM = 0. >> >> Bit 2: SDV_ENABLE_RTM (new bit, default=0) When clear, XBEGIN will >> always abort with EAX code 0. When set, XBEGIN will not be forced to >> abort (but will always abort in SGX enclaves). This bit is intended to >> be SDV-only. If this bit is set transactional atomicity correctness is > >SDV?
Sorry should have expanded this. It stands for Software Development Vehicle (SDV), i.e. developer systems.
>> not certain. >> >> Performance monitoring counter 3 is usable in all cases, regardless of >> the value of above bits. >> >> A new CPUID bit CPUID.RTM_ALWAYS_ABORT (CPUID 7.EDX[11]) is added to >> indicate the status of always abort behavior. >> >> Define these new CPUID and MSR bits. >> >> [1] Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory >> http://cdrdv2.intel.com/v1/dl/getContent/604224 > >That link does not look stable enough to put in commit messages. >Besides, you've said it all in the commit message already.
The important part is the Document ID 604224. I can remove the link completely, or add the document ID to it, whatever you suggest:
[1] Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory http://cdrdv2.intel.com/v1/dl/getContent/604224 (Document ID 604224). ^^^^^^^^^^^^^^^^^^
Thanks, Pawan
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