Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Thu, 10 Jun 2021 14:31:16 +0200 | Subject | Re: [PATCH v3 06/11] clk: renesas: Define RZ/G2L CPG Clock Definitions |
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On Wed, Jun 9, 2021 at 5:33 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock > and module clock outputs, as listed in Table 8.3 ("Clock List") > of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021). > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.14.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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