Messages in this thread | | | From | "Lad, Prabhakar" <> | Date | Thu, 27 May 2021 12:47:14 +0100 | Subject | Re: [PATCH 01/16] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC |
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Hi Geert,
On Thu, May 27, 2021 at 12:29 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Fri, May 21, 2021 at 6:54 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Fri, May 21, 2021 at 2:23 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > Add device tree bindings documentation for Renesas RZ/G2UL SoC. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > > > > > Thanks for your patch! > > > > > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > > > @@ -302,6 +302,12 @@ properties: > > > > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > > > > - const: renesas,r9a06g032 > > > > > > > > + - description: RZ/G2UL (R9A07G043) > > > > + items: > > > > + - enum: > > > > + - renesas,r9a07g043u11 # Single Cortex-A55 RZ/G2UL > > > > > > Is there any specific reason you're including the final "1", unlike the > > > RZ/G2{L,LC} binding? > > > > > To be consistent with the RZ/G2L family of SoC's "1" is appended to > > the compatible string. > My bad, the reason for adding 1 in the end was there are two variants of RZ/G2UL [1]. For the next respin I'll include renesas,r9a07g043u12 too.
> No, for RZ/G2L you have: > > renesas,r9a07g044c1 for r9a07g044c12 > renesas,r9a07g044c2 for r9a07g044c22 > renesas,r9a07g044l1 for r9a07g044l13 and r9a07g044l14 > renesas,r9a07g044l2 for r9a07g044l23 and r9a07g044l24 > > i.e. the compatible value lacks the final digit. > > For RZ/G2UL, I do not know if we have to distinguish between > r9a07g043u11 and r9a07g043u12. > Some IP blocks are missing in type2 compared to type1. And at the higher level we might want to know the exact SoC type the board is built ?
> > > As RZ/G2UL is always single-core, perhaps this compatible value can be > > > dropped? > > > > > Do agree with you. > > In light of the continued discussion for [PATCH 02/16], perhaps it's > good to keep it anyway? > Yes will keep the compatible string.
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-arm-based-high-end-32-64-bit-mpus/rzg2ul-general-purpose-microprocessors-single-core-arm-cortex-a55-10-ghz-cpu-2ch-giga-bit-ethernet
Cheers, Prabhakar
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