Messages in this thread Patch in this message | | | From | Nobuhiro Iwamatsu <> | Subject | [PATCH 3/4] dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV7700 SoC | Date | Tue, 25 May 2021 17:46:54 +0900 |
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Add device tree bindings for SMU (System Management Unit) controller of Toshiba Visconti TMPV7700 SoC series.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- .../clock/toshiba,tmpv7708-pismu.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tmpv7708-pismu.yaml
diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv7708-pismu.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv7708-pismu.yaml new file mode 100644 index 000000000000..7a8eac00e624 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv7708-pismu.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tmpv7708-pismu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 TMPV7708 SMU controller Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: + Toshia Visconti5 PLL controller which supports the clock and resets on + TMPV7708. + +properties: + compatible: + const: toshiba,tmpv7708-pismu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pismu: pismu@24200000 { + compatible = "toshiba,tmpv7708-pismu"; + reg = <0 0x24200000 0 0x2140>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +... -- 2.31.1
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