Messages in this thread | | | From | Martin Blumenstingl <> | Date | Mon, 24 May 2021 13:49:33 +0200 | Subject | Re: [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel |
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Hi Jerome,
On Mon, May 24, 2021 at 12:57 PM Jerome Brunet <jbrunet@baylibre.com> wrote: > > > On Mon 24 May 2021 at 12:45, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > > MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent > > list so we only use the (mutable) vid_pll_final_div tree or one of the > > (fixed) FCLK_DIV{3,4,5} clocks. > > Are the fixed ones actually needed ? > > If the consumer actually lives on the vid_pll only, I'd prefer if you > could add CLK_SET_RATE_NOREPARENT and assign the proper parent in DT with > `assigned-clock-parents` you're right, only the vid_pll_final_div tree is used I just tested it with assigned-clock-parents and CLK_SET_RATE_NO_REPARENT and it's working fine. I'll send a v2 later today
Thanks for this suggestion!
Best regards, Martin
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