Messages in this thread | | | Subject | Re: [PATCH] clk: meson: g12a: fix gp0 and hifi ranges | From | Neil Armstrong <> | Date | Thu, 20 May 2021 16:02:40 +0200 |
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On 29/04/2021 11:03, Jerome Brunet wrote: > While some SoC samples are able to lock with a PLL factor of 55, others > samples can't. ATM, a minimum of 60 appears to work on all the samples > I have tried. > > Even with 60, it sometimes takes a long time for the PLL to eventually > lock. The documentation says that the minimum rate of these PLLs DCO > should be 3GHz, a factor of 125. Let's use that to be on the safe side. > > With factor range changed, the PLL seems to lock quickly (enough) so far. > It is still unclear if the range was the only reason for the delay. > > Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > drivers/clk/meson/g12a.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > index b080359b4645..a805bac93c11 100644 > --- a/drivers/clk/meson/g12a.c > +++ b/drivers/clk/meson/g12a.c > @@ -1603,7 +1603,7 @@ static struct clk_regmap g12b_cpub_clk_trace = { > }; > > static const struct pll_mult_range g12a_gp0_pll_mult_range = { > - .min = 55, > + .min = 125, > .max = 255, > }; > >
Sorry for bothering with the DSI stuff, I'll fix this when we are ready to upstream DSI support for G12A.
I had this patch for a while in my integration branches, so: Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Neil
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