Messages in this thread | | | From | Jerome Brunet <> | Subject | Re: [PATCH RFC v1 3/3] clk: meson: pll: switch to determine_rate for the PLL ops | Date | Wed, 19 May 2021 17:10:26 +0200 |
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On Tue 18 May 2021 at 22:17, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> Hi Jerome, > > On Tue, May 18, 2021 at 9:50 AM Jerome Brunet <jbrunet@baylibre.com> wrote: >> >> >> On Mon 17 May 2021 at 22:37, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: >> >> > This increases the maxmium supported frequency on 32-bit systems from >> > 2^31 (signed long as used by clk_ops.round_rate, maximum value: >> > approx. 2.14GHz) to 2^32 (unsigned long as used by >> > clk_ops.determine_rate, maximum value: approx. 4.29GHz). >> > On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are >> > capable of running at up to 2.97GHz. So switch the divider >> > implementation in clk-regmap to clk_ops.determine_rate to support these >> > higher frequencies on 32-bit systems. >> > >> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> >> >> Looks good. I see no reason to keep this one as RFC. > Great, thanks for checking! > >> I can take it directly if this is OK with you ? > That would be amazing. > Obviously no objections from my side :-) > > > Best regards, > Martin
Applied then. Thx
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