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Subject[PATCH] openrisc: Define memory barrier mb
From: Peter Zijlstra <>

This came up in the discussion of the requirements of qspinlock on an
architecture. OpenRISC uses qspinlock, but it was noticed that the
memmory barrier was not defined.

Peter defined it in the mail thread writing:

As near as I can tell this should do. The arch spec only lists
this one instruction and the text makes it sound like a completion

This is correct so applying this patch.

Signed-off-by: Peter Zijlstra <>
[ the mail into a patch]
Signed-off-by: Stafford Horne <>
I just applied the patch posted by Peter in the mail as is hence it is labeled
from peter. This also required me to set the Signed-off-by to Peter.

If there is any issue with that let me know. I tested this out on my single
processor setup and it all works fine, it will take me some time to get my SMP
setup up and running again to test the other patches, but I figured I would send
this patch first.

Also, I got delayed because I had to rebuild my main workstation after a
hardware failure.

arch/openrisc/include/asm/barrier.h | 9 +++++++++
1 file changed, 9 insertions(+)
create mode 100644 arch/openrisc/include/asm/barrier.h

diff --git a/arch/openrisc/include/asm/barrier.h b/arch/openrisc/include/asm/barrier.h
new file mode 100644
index 000000000000..7538294721be
--- /dev/null
+++ b/arch/openrisc/include/asm/barrier.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+#define mb() asm volatile ("l.msync" ::: "memory")
+#include <asm-generic/barrier.h>
+#endif /* __ASM_BARRIER_H */
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