Messages in this thread Patch in this message | | | Date | Thu, 13 May 2021 13:29:30 +0100 | From | Paul Cercueil <> | Subject | Re: [PATCH] drm/ingenic: Fix pixclock rate for 24-bit serial panels |
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Hi,
Almost two months later,
Le mar., mars 23 2021 at 14:40:08 +0000, Paul Cercueil <paul@crapouillou.net> a écrit : > When using a 24-bit panel on a 8-bit serial bus, the pixel clock > requested by the panel has to be multiplied by 3, since the subpixels > are shifted sequentially. > > The code (in ingenic_drm_encoder_atomic_check) already computed > crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate() > used crtc_state->adjusted_mode->clock instead. > > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when > using a 3x8-bit panel") > Cc: stable@vger.kernel.org # v5.10 > Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Can I get an ACK for my patch?
Thanks! -Paul
> --- > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index d60e1eefc9d1..cba68bf52ec5 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct > drm_crtc *crtc, > if (priv->update_clk_rate) { > mutex_lock(&priv->clk_mutex); > clk_set_rate(priv->pix_clk, > - crtc_state->adjusted_mode.clock * 1000); > + crtc_state->adjusted_mode.crtc_clock * 1000); > priv->update_clk_rate = false; > mutex_unlock(&priv->clk_mutex); > } > -- > 2.30.2 >
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