Messages in this thread | | | Date | Wed, 12 May 2021 10:37:37 +0200 | From | Peter Zijlstra <> | Subject | Re: [patch 1/2 v2] x86/cpu: Init AP exception handling from cpu_init_secondary() |
| |
On Tue, May 11, 2021 at 05:25:35PM +0800, Lai Jiangshan wrote: > > > On 2021/5/11 05:29, Thomas Gleixner wrote: > > From: Borislav Petkov <bp@suse.de> > > > > SEV-ES guests require properly setup task register with which the TSS > > descriptor in the GDT can be located so that the IST-type #VC exception > > handler which they need to function properly, can be executed. > > > > This setup needs to happen before attempting to load microcode in > > ucode_cpu_init() on secondary CPUs which can cause such #VC exceptions. > > > > Simplify the machinery by running that exception setup from a new function > > cpu_init_secondary() and explicitly call cpu_init_exception_handling() for > > the boot CPU before cpu_init(). The latter prepares for fixing and > > simplifying the exception/IST setup on the boot CPU. > > > > There should be no functional changes resulting from this patch. > > > > [ tglx: Reworked it so cpu_init_exception_handling() stays seperate ] > > > > Signed-off-by: Borislav Petkov <bp@suse.de> > > Signed-off-by: Thomas Gleixner <tglx@linutronix.de> > > > For both patches: > > Reviewed-by: Lai Jiangshan <laijs@linux.alibaba.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
| |