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    Subject[PATCH 5.11 210/601] arm64: dts: renesas: r8a779a0: Fix PMU interrupt
    Date
    From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

    [ Upstream commit bbbf6db5a0b56199702bb225132831bced2eee41 ]

    Should use PPI No.7 for the PMU. Otherwise, the perf command didn't
    show any information.

    Fixes: 834c310f5418 ("arm64: dts: renesas: Add Renesas R8A779A0 SoC support")
    Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
    Link: https://lore.kernel.org/r/20210325041949.925777-1-yoshihiro.shimoda.uh@renesas.com
    Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 5 +----
    1 file changed, 1 insertion(+), 4 deletions(-)

    diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
    index 6cf77ce9aa93..86ec32a919d2 100644
    --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
    @@ -50,10 +50,7 @@

    pmu_a76 {
    compatible = "arm,cortex-a76-pmu";
    - interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
    - <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
    - <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
    - <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
    + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
    };

    /* External SCIF clock - to be overridden by boards that provide it */
    --
    2.30.2


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