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    Subject[PATCH 5.11 132/601] ARM: dts: exynos: correct MUIC interrupt trigger level on Midas family
    Date
    From: Krzysztof Kozlowski <krzk@kernel.org>

    [ Upstream commit 15107e443ab8c6cb35eff10438993e4bc944d9ae ]

    The Maxim MUIC datasheets describe the interrupt line as active low
    with a requirement of acknowledge from the CPU. Without specifying the
    interrupt type in Devicetree, kernel might apply some fixed
    configuration, not necessarily working for this hardware.

    Additionally, the interrupt line is shared so using level sensitive
    interrupt is here especially important to avoid races.

    Fixes: 7eec1266751b ("ARM: dts: Add Maxim 77693 PMIC to exynos4412-trats2")
    Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
    Link: https://lore.kernel.org/r/20201210212534.216197-4-krzk@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm/boot/dts/exynos4412-midas.dtsi | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
    index b8b75dc81aa1..d75f554efde0 100644
    --- a/arch/arm/boot/dts/exynos4412-midas.dtsi
    +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
    @@ -173,7 +173,7 @@
    pmic@66 {
    compatible = "maxim,max77693";
    interrupt-parent = <&gpx1>;
    - interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
    + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
    pinctrl-names = "default";
    pinctrl-0 = <&max77693_irq>;
    reg = <0x66>;
    --
    2.30.2


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