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    Subject[PATCH 5.10 392/530] iommu/vt-d: Preset Access/Dirty bits for IOVA over FL
    Date
    From: Lu Baolu <baolu.lu@linux.intel.com>

    [ Upstream commit a8ce9ebbecdfda3322bbcece6b3b25888217f8e3 ]

    The Access/Dirty bits in the first level page table entry will be set
    whenever a page table entry was used for address translation or write
    permission was successfully translated. This is always true when using
    the first-level page table for kernel IOVA. Instead of wasting hardware
    cycles to update the certain bits, it's better to set them up at the
    beginning.

    Suggested-by: Ashok Raj <ashok.raj@intel.com>
    Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
    Link: https://lore.kernel.org/r/20210115004202.953965-1-baolu.lu@linux.intel.com
    Signed-off-by: Joerg Roedel <jroedel@suse.de>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iommu/intel/iommu.c | 17 ++++++++++++-----
    include/linux/intel-iommu.h | 2 ++
    2 files changed, 14 insertions(+), 5 deletions(-)

    diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
    index 3295e5e162a4..8010c3895f8c 100644
    --- a/drivers/iommu/intel/iommu.c
    +++ b/drivers/iommu/intel/iommu.c
    @@ -1028,8 +1028,11 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,

    domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
    pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
    - if (domain_use_first_level(domain))
    + if (domain_use_first_level(domain)) {
    pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
    + if (domain->domain.type == IOMMU_DOMAIN_DMA)
    + pteval |= DMA_FL_PTE_ACCESS;
    + }
    if (cmpxchg64(&pte->val, 0ULL, pteval))
    /* Someone else set it while we were thinking; use theirs. */
    free_pgtable_page(tmp_page);
    @@ -2354,14 +2357,18 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
    return -EINVAL;

    attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);
    - if (domain_use_first_level(domain))
    + if (domain_use_first_level(domain)) {
    attr |= DMA_FL_PTE_PRESENT | DMA_FL_PTE_XD | DMA_FL_PTE_US;

    - if (!sg) {
    - sg_res = nr_pages;
    - pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | attr;
    + if (domain->domain.type == IOMMU_DOMAIN_DMA) {
    + attr |= DMA_FL_PTE_ACCESS;
    + if (prot & DMA_PTE_WRITE)
    + attr |= DMA_FL_PTE_DIRTY;
    + }
    }

    + pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | attr;
    +
    while (nr_pages > 0) {
    uint64_t tmp;

    diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
    index 94522685a0d9..ccaa057faf8c 100644
    --- a/include/linux/intel-iommu.h
    +++ b/include/linux/intel-iommu.h
    @@ -42,6 +42,8 @@

    #define DMA_FL_PTE_PRESENT BIT_ULL(0)
    #define DMA_FL_PTE_US BIT_ULL(2)
    +#define DMA_FL_PTE_ACCESS BIT_ULL(5)
    +#define DMA_FL_PTE_DIRTY BIT_ULL(6)
    #define DMA_FL_PTE_XD BIT_ULL(63)

    #define ADDR_WIDTH_5LEVEL (57)
    --
    2.30.2


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