Messages in this thread | | | Subject | Re: [PATCH v5 0/5] perf/x86: Some minor changes to support guest Arch LBR | From | Like Xu <> | Date | Fri, 9 Apr 2021 16:51:02 +0800 |
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Em, does anyone want to review these minor changes?
I believe some of them solve the real problem.
On 2021/4/6 11:20, Like Xu wrote: > Hi all, do we have any comments on this patch set? > > On 2021/3/26 9:19, Like Xu wrote: >> Hi Peter, >> >> Please help review these minor perf/x86 changes in this patch set, >> and we need some of them to support Guest Architectural LBR in KVM. >> >> This version keeps reserve_lbr_buffers() as is because the LBR xsave >> buffer is a per-CPU buffer, not a per-event buffer. We only need to >> allocate the buffer once when initializing the first event. >> >> If you are interested in the KVM emulation, please check >> https://lore.kernel.org/kvm/20210314155225.206661-1-like.xu@linux.intel.com/ >> >> Please check more details in each commit and feel free to comment. >> >> Previous: >> https://lore.kernel.org/lkml/20210322060635.821531-1-like.xu@linux.intel.com/ >> >> >> v4->v5 Changelog: >> - Add "Tested-by: Kan Liang" >> - Make the commit message simpler >> - Make check_msr() to ignore msr==0 >> - Use kmem_cache_alloc_node() [Namhyung] >> >> Like Xu (5): >> perf/x86/intel: Fix the comment about guest LBR support on KVM >> perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers >> perf/x86: Skip checking MSR for MSR 0x000 >> perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region >> perf/x86: Move ARCH_LBR_CTL_MASK definition to include/asm/msr-index.h >> >> arch/x86/events/core.c | 8 +++++--- >> arch/x86/events/intel/bts.c | 2 +- >> arch/x86/events/intel/core.c | 7 +++---- >> arch/x86/events/intel/lbr.c | 29 ++++++++++++++++++----------- >> arch/x86/events/perf_event.h | 8 +++++++- >> arch/x86/include/asm/msr-index.h | 1 + >> 6 files changed, 35 insertions(+), 20 deletions(-) >> >
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