Messages in this thread | | | Subject | Re: [OpenRISC] [PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 | From | Waiman Long <> | Date | Thu, 8 Apr 2021 15:00:59 -0400 |
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On 4/6/21 7:52 PM, Stafford Horne wrote: > > For OpenRISC I did ack the patch to convert to > CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32=y. But I think you are right, the > generic code in xchg_tail and the xchg16 emulation code in produced by OpenRISC > using xchg32 would produce very similar code. I have not compared instructions, > but it does seem like duplicate functionality. > > Why doesn't RISC-V add the xchg16 emulation code similar to OpenRISC? For > OpenRISC we added xchg16 and xchg8 emulation code to enable qspinlocks. So > one thought is with CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32=y, can we remove our > xchg16/xchg8 emulation code?
For the record, the latest qspinlock code doesn't use xchg8 anymore. It still need xchg16, though.
Cheers, Longman
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