Messages in this thread | | | Subject | Re: [PATCH] clk: exynos7: Mark aclk_fsys1_200 as critical | From | Sylwester Nawrocki <> | Date | Wed, 7 Apr 2021 12:03:39 +0200 |
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On 24.10.2020 17:43, Paweł Chmiel wrote: > This clock must be always enabled to allow access to any registers in > fsys1 CMU. Until proper solution based on runtime PM is applied > (similar to what was done for Exynos5433), mark that clock as critical > so it won't be disabled. > > It was observed on Samsung Galaxy S6 device (based on Exynos7420), where > UFS module is probed before pmic used to power that device. > In this case defer probe was happening and that clock was disabled by > UFS driver, causing whole boot to hang on next CMU access. > > Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> > --- > drivers/clk/samsung/clk-exynos7.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c > index c1ff715e960c..1048d83f097b 100644 > --- a/drivers/clk/samsung/clk-exynos7.c > +++ b/drivers/clk/samsung/clk-exynos7.c > @@ -538,7 +538,8 @@ static const struct samsung_gate_clock top1_gate_clks[] __initconst = { > ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT | > CLK_IS_CRITICAL, 0),
As this patch can be backported up to the commit that introduced regression I have applied it instead of your v3, with a comment as below.
+ /* + * This clock is required for the CMU_FSYS1 registers access, keep it + * enabled permanently until proper runtime PM support is added. + */
> GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", > - ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), > + ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT | > + CLK_IS_CRITICAL, 0), > > GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m", > "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11, -- Regards, Sylwester
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