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    Subject[PATCH 2/4] perf vendor events amd: Use lowercases for all the eventcodes and umasks
    Date
    The values of event codes and umasks are inconsistent with letter cases.
    Enforce a unique style and default everything to lower case as this helps
    in tracking changes of automatically generated event tables.

    Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
    Reviewed-by: Robert Richter <rrichter@amd.com>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Namhyung Kim <namhyung@kernel.org>
    Cc: Ian Rogers <irogers@google.com>
    Cc: Vijay Thakkar <vijaythakkar@me.com>
    Cc: Martin Liška <mliska@suse.cz>
    Cc: Michael Petlan <mpetlan@redhat.com>
    Cc: Kim Phillips <kim.phillips@amd.com>
    Cc: linux-perf-users@vger.kernel.org
    ---
    .../perf/pmu-events/arch/x86/amdzen2/branch.json | 2 +-
    .../perf/pmu-events/arch/x86/amdzen2/cache.json | 2 +-
    .../perf/pmu-events/arch/x86/amdzen2/memory.json | 16 ++++++++--------
    3 files changed, 10 insertions(+), 10 deletions(-)

    diff --git a/tools/perf/pmu-events/arch/x86/amdzen2/branch.json b/tools/perf/pmu-events/arch/x86/amdzen2/branch.json
    index ef4166a66288..f5d16846aa1d 100644
    --- a/tools/perf/pmu-events/arch/x86/amdzen2/branch.json
    +++ b/tools/perf/pmu-events/arch/x86/amdzen2/branch.json
    @@ -24,7 +24,7 @@
    "EventName": "bp_l1_tlb_fetch_hit",
    "EventCode": "0x94",
    "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.",
    - "UMask": "0xFF"
    + "UMask": "0xff"
    },
    {
    "EventName": "bp_l1_tlb_fetch_hit.if1g",
    diff --git a/tools/perf/pmu-events/arch/x86/amdzen2/cache.json b/tools/perf/pmu-events/arch/x86/amdzen2/cache.json
    index 8ba84a48188d..899ccc81263c 100644
    --- a/tools/perf/pmu-events/arch/x86/amdzen2/cache.json
    +++ b/tools/perf/pmu-events/arch/x86/amdzen2/cache.json
    @@ -353,7 +353,7 @@
    },
    {
    "EventName": "xi_ccx_sdp_req1.all_l3_miss_req_typs",
    - "EventCode": "0x9A",
    + "EventCode": "0x9a",
    "BriefDescription": "All L3 Miss Request Types. Ignores SliceMask and ThreadMask.",
    "UMask": "0x3f",
    "Unit": "L3PMC"
    diff --git a/tools/perf/pmu-events/arch/x86/amdzen2/memory.json b/tools/perf/pmu-events/arch/x86/amdzen2/memory.json
    index 715046b339cb..609d9e3da3f7 100644
    --- a/tools/perf/pmu-events/arch/x86/amdzen2/memory.json
    +++ b/tools/perf/pmu-events/arch/x86/amdzen2/memory.json
    @@ -60,17 +60,17 @@
    },
    {
    "EventName": "ls_smi_rx",
    - "EventCode": "0x2B",
    + "EventCode": "0x2b",
    "BriefDescription": "Number of SMIs received."
    },
    {
    "EventName": "ls_int_taken",
    - "EventCode": "0x2C",
    + "EventCode": "0x2c",
    "BriefDescription": "Number of interrupts taken."
    },
    {
    "EventName": "ls_rdtsc",
    - "EventCode": "0x2D",
    + "EventCode": "0x2d",
    "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
    },
    {
    @@ -300,31 +300,31 @@
    },
    {
    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram",
    - "EventCode": "0x5A",
    + "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
    "UMask": "0x40"
    },
    {
    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache",
    - "EventCode": "0x5A",
    + "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
    "UMask": "0x10"
    },
    {
    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram",
    - "EventCode": "0x5A",
    + "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local).",
    "UMask": "0x8"
    },
    {
    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache",
    - "EventCode": "0x5A",
    + "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
    "UMask": "0x2"
    },
    {
    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2",
    - "EventCode": "0x5A",
    + "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit.",
    "UMask": "0x1"
    },
    --
    2.17.1
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