Messages in this thread | | | Date | Thu, 29 Apr 2021 18:28:13 +0200 | From | Michael Walle <> | Subject | Re: [RFC PATCH 4/6] spi: cadence-qspi: Use PHY for DAC reads if possible |
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Am 2021-03-12 11:17, schrieb Pratyush Yadav: > On 12/03/21 09:13AM, Tudor.Ambarus@microchip.com wrote: >> On 3/11/21 9:12 PM, Pratyush Yadav wrote: >> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> > >> > Check if a read is eligible for PHY and if it is, enable PHY and DQS. >> >> DQS as in data strobe? Shouldn't the upper layer inform the QSPI >> controller >> whether DS is required or not? > > Yes, DQS as in data strobe. I need to check this again, but IIRC the > controller cannot run in PHY mode unless DS is used. Ideally the upper > layer should indeed inform the controller whether DS is > supported/in-use > or not. That can be used to decide whether PHY mode (and consequently > the DS line) is to be used or not. > > Currently there are only two flashes that use 8D-8D-8D mode (S28HS512T > and MT35XU512ABA), and both of them drive the DS line.
The LS1028A datasheet explicitly states that the calibration is only used for non-DQS flashes. Which makes sense, because it just determine at which point the input data is sampled. And if the flash provides a data strobe, it already know when to sample it. What I am missing here?
-michael
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