Messages in this thread | | | From | Nava kishore Manne <> | Subject | RE: [PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config driver | Date | Thu, 29 Apr 2021 05:39:43 +0000 |
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Hi Rob,
Thanks for the review. Please find my response inline.
> -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Tuesday, April 20, 2021 7:45 PM > To: Nava kishore Manne <navam@xilinx.com> > Cc: Michal Simek <michals@xilinx.com>; Derek Kiernan > <dkiernan@xilinx.com>; Dragan Cvetic <draganc@xilinx.com>; > arnd@arndb.de; gregkh@linuxfoundation.org; Rajan Vaja > <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; Tejas Patel > <tejasp@xlnx.xilinx.com>; Amit Sunil Dhamne <amitsuni@xilinx.com>; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; chinnikishore369@gmail.com; git <git@xilinx.com> > Subject: Re: [PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config > driver > > On Tue, Apr 20, 2021 at 01:41:52PM +0530, Nava kishore Manne wrote: > > This patch adds the binding document for the zynqmp afi config driver. > > Bindings are for h/w blocks, not drivers. >
This Binding are for h/w blocks (PS-PL bus width configurations) For more info please refer the below links. https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf (Page No: 54) https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e/v3_2/pg201-zynq-ultrascale-plus-processing-system.pdf (Page No: 42).
Please let me know if you need more info..
> > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > > --- > > .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++ > > 1 file changed, 136 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml > > b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml > > new file mode 100644 > > index 000000000000..3ae22096b22a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi- > fpga.yaml > > @@ -0,0 +1,136 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Xilinx ZynqMP AFI interface Manager. > > + > > +maintainers: > > + - Nava kishore Manne <nava.manne@xilinx.com> > > + > > +description: | > > + The Zynq UltraScale+ MPSoC Processing System core provides access > > +from PL > > + masters to PS internal peripherals, and memory through AXI FIFO > > +interface(AFI) > > + interfaces. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - xlnx,zynqmp-afi-fpga > > + > > + config-afi: > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + description: | > > + Pairs of <regid value > > > + The possible values of regid and values are > > + regid - Regids of the register to be written possible values > > If we wanted sequences of register accesses in DT, we'd have a generic > mechanism to do so. >
I will try to find a better way, will get back you on this
Regards, Navakishore.
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