lkml.org 
[lkml]   [2021]   [Apr]   [27]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Date
SubjectRe: [PATCH] arm64: perf: Ensure EL0 access is disabled at reset
On Tue, Apr 27, 2021 at 8:55 AM Mark Rutland <mark.rutland@arm.com> wrote:
>
> On Tue, Apr 27, 2021 at 08:48:52AM -0500, Rob Herring wrote:
> > The ER, SW, and EN bits in the PMUSERENR_EL0 register are UNKNOWN at
> > reset and the register is never initialized, so EL0 access could be
> > enabled by default on some implementations. Let's initialize
> > PMUSERENR_EL0 to a known state with EL0 access disabled.
>
> We reset PMUSERENR_EL0 via the reset_pmuserenr_el0 macro, called from
> __cpu_setup when a CPU is onlined and from cpu_do_resume() when a CPU
> returns from a context-destructive idle state. We do it there so that
> it's handled even if a kernel isn't built with perf support.

Indeed.

> AFAICT, that *should* do the right thing -- are you seeing UNKNOWN
> values, or was this found by inspection?

Inspection. Sorry for the noise.

Rob

\
 
 \ /
  Last update: 2021-04-27 16:06    [W:0.066 / U:0.032 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site