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    Subject[PATCH 5.11 06/41] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish
    Date
    From: Jiansong Chen <Jiansong.Chen@amd.com>

    commit 24d034528ef06ad94cfcf4394beac0443ab1b16d upstream.

    dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,
    so follow its registers offset setting.

    Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
    Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
    @@ -3280,7 +3280,7 @@ static const struct soc15_reg_golden gol
    SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
    SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
    SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
    - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
    + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
    SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
    SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
    SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),

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