Messages in this thread Patch in this message | | | From | Sherry Sun <> | Subject | [PATCH V2] tty: serial: fsl_lpuart: fix the potential risk of division or modulo by zero | Date | Tue, 27 Apr 2021 10:12:26 +0800 |
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We should be very careful about the register values that will be used for division or modulo operations, althrough the possibility that the UARTBAUD register value is zero is very low, but we had better to deal with the "bad data" of hardware in advance to avoid division or modulo by zero leading to undefined kernel behavior.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com> --- V2: Amend commit message according to the review suggestions for better understand the change. --- drivers/tty/serial/fsl_lpuart.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 794035041744..777d54b593f8 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -2414,6 +2414,9 @@ lpuart32_console_get_options(struct lpuart_port *sport, int *baud, bd = lpuart32_read(&sport->port, UARTBAUD); bd &= UARTBAUD_SBR_MASK; + if (!bd) + return; + sbr = bd; uartclk = lpuart_get_baud_clk_rate(sport); /* -- 2.17.1
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