Messages in this thread | | | Subject | Re: [PATCH v1 4/5] arm64: dts: rockchip: add core dtsi for RK3568 SoC | From | 陈亮 <> | Date | Sun, 25 Apr 2021 17:16:50 +0800 |
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Hi Marc,
Thanks for reply.
See below.
在 2021/4/21 下午9:36, Marc Zyngier 写道: > On Wed, 21 Apr 2021 07:59:20 +0100, > <cl@rock-chips.com> wrote: >> From: Liang Chen <cl@rock-chips.com> >> >> RK3568 is a high-performance and low power quad-core application processor >> designed for personal mobile internet device and AIoT equipments. >> >> This patch add basic core dtsi file for it. >> >> Signed-off-by: Liang Chen <cl@rock-chips.com> >> --- >> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 2789 +++++++++++++++++ >> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 795 +++++ >> .../boot/dts/rockchip/rockchip-pinconf.dtsi | 346 ++ >> 3 files changed, 3930 insertions(+) >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi >> create mode 100644 arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi >> > [...] > >> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi >> new file mode 100644 >> index 000000000000..ac8db2f54f2b >> --- /dev/null >> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi >> @@ -0,0 +1,795 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. >> + */ >> + >> +#include <dt-bindings/clock/rk3568-cru.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/pinctrl/rockchip.h> >> +#include <dt-bindings/soc/rockchip,boot-mode.h> >> +#include <dt-bindings/phy/phy.h> >> +#include <dt-bindings/thermal/thermal.h> >> + >> +/ { >> + compatible = "rockchip,rk3568"; >> + >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + aliases { >> + serial2 = &uart2; >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + clocks = <&scmi_clk 0>; >> + operating-points-v2 = <&cpu0_opp_table>; >> + #cooling-cells = <2>; >> + }; >> + cpu1: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x100>; >> + enable-method = "psci"; >> + operating-points-v2 = <&cpu0_opp_table>; >> + }; >> + cpu2: cpu@200 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x200>; >> + enable-method = "psci"; >> + operating-points-v2 = <&cpu0_opp_table>; >> + }; >> + cpu3: cpu@300 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x300>; >> + enable-method = "psci"; >> + operating-points-v2 = <&cpu0_opp_table>; >> + }; >> + }; >> + >> + cpu0_opp_table: cpu0-opp-table { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp-408000000 { >> + opp-hz = /bits/ 64 <408000000>; >> + opp-microvolt = <825000 825000 1150000>; >> + clock-latency-ns = <40000>; >> + }; >> + opp-600000000 { >> + opp-hz = /bits/ 64 <600000000>; >> + opp-microvolt = <825000 825000 1150000>; >> + }; >> + opp-816000000 { >> + opp-hz = /bits/ 64 <816000000>; >> + opp-microvolt = <825000 825000 1150000>; >> + opp-suspend; >> + }; >> + opp-1104000000 { >> + opp-hz = /bits/ 64 <1104000000>; >> + opp-microvolt = <825000 825000 1150000>; >> + }; >> + opp-1416000000 { >> + opp-hz = /bits/ 64 <1416000000>; >> + opp-microvolt = <900000 900000 1150000>; >> + }; >> + opp-1608000000 { >> + opp-hz = /bits/ 64 <1608000000>; >> + opp-microvolt = <975000 975000 1150000>; >> + }; >> + opp-1800000000 { >> + opp-hz = /bits/ 64 <1800000000>; >> + opp-microvolt = <1050000 1050000 1150000>; >> + }; >> + opp-1992000000 { >> + opp-hz = /bits/ 64 <1992000000>; >> + opp-microvolt = <1150000 1150000 1150000>; >> + }; >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; >> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; >> + }; >> + >> + firmware { >> + scmi: scmi { >> + compatible = "arm,scmi-smc"; >> + shmem = <&scmi_shmem>; >> + arm,smc-id = <0x82000010>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + scmi_clk: protocol@14 { >> + reg = <0x14>; >> + #clock-cells = <1>; >> + }; >> + }; >> + >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > This doesn't match the GICv3 binding for PPIs. fixed in V2. > >> + arm,no-tick-in-suspend; > Oh, really? :-( yes, arm arch timer will stop in suspend mode on rk3568. > >> + }; >> + >> + xin24m: xin24m { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <24000000>; >> + clock-output-names = "xin24m"; >> + }; >> + >> + xin32k: xin32k { >> + compatible = "fixed-clock"; >> + clock-frequency = <32768>; >> + clock-output-names = "xin32k"; >> + #clock-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&clk32k_out0>; >> + }; >> + >> + scmi_shmem: scmi-shmem@10f000 { >> + compatible = "arm,scmi-shmem"; >> + reg = <0x0 0x0010f000 0x0 0x100>; >> + }; >> + >> + gic: interrupt-controller@fd400000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + interrupt-controller; >> + >> + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ >> + <0x0 0xfd460000 0 0xc0000>; /* GICR */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > Please add the 'mbi-alias' property, which should map onto the GICA > range that GIC600 provides. At least this could be useful to have MSIs > despite the lack of a working ITS. We can work out the usable ranges > on a per-board basis.
Thanks, we will try mbi-alias later, but we are afraid that the number of SPI is not enough.
> > Thanks, > > M. >
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