Messages in this thread | | | Subject | Re: [v2 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control. | From | Randy Dunlap <> | Date | Thu, 22 Apr 2021 10:49:10 -0700 |
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On 4/22/21 10:10 AM, Ramakrishna Saripalli wrote: > From: Ramakrishna Saripalli <rk.saripalli@amd.com> > > ==================== > Signed-off-by: Ramakrishna Saripalli<rk.saripalli@amd.com> > --- > .../admin-guide/kernel-parameters.txt | 5 +++++ > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/msr-index.h | 2 ++ > arch/x86/kernel/cpu/amd.c | 19 +++++++++++++++++++ > 4 files changed, 27 insertions(+)
as from v1:
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 04545725f187..58f6bd02385b 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -3940,6 +3940,11 @@ > Format: {"off"} > Disable Hardware Transactional Memory > > + predict_store_fwd [X86] This option controls PSF mitigation
predict_store_fwd= ...
> + off - Turns on PSF mitigation. > + on - Turns off PSF mitigation. > + default : on.
default: on.
> + > preempt= [KNL] > Select preemption mode if you have CONFIG_PREEMPT_DYNAMIC > none - Limited to cond_resched() calls thanks. -- ~Randy
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