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Subject[PATCH] dt-bindings: pinctrl: rockchip: Convert to json-schema
Date
Convert the pinctrl/rockchip,pinctrl.txt binding document to
json-schema.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
.../bindings/pinctrl/rockchip,pinctrl.yaml | 163 ++++++++++++++++++
1 file changed, 163 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
new file mode 100644
index 000000000000..59cddcd30dbc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/rockchip,rockchip-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Pinmux Controller
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The Rockchip Pinmux Controller, enables the IC
+ to share one PAD to several functional blocks. The sharing is done by
+ multiplexing the PAD input/output signals. For each PAD there are several
+ muxing options with option 0 being the use as a GPIO.
+
+ Please refer to pinctrl-bindings.txt in this directory for details of the
+ common pinctrl bindings used by client devices, including the meaning of the
+ phrase "pin configuration node".
+
+ The Rockchip pin configuration node is a node of a group of pins which can be
+ used for a specific device or function. This node represents both mux and
+ config of the pins in that group. The 'pins' selects the function mode(also
+ named pin mode) this pin can work on and the 'config' configures various pad
+ settings such as pull-up, etc.
+
+ The pins are grouped into up to 5 individual pin banks which need to be
+ defined as gpio sub-nodes of the pinmux controller.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-pinctrl
+ - rockchip,rv1108-pinctrl
+ - rockchip,rk2928-pinctrl
+ - rockchip,rk3066a-pinctrl
+ - rockchip,rk3066b-pinctrl
+ - rockchip,rk3128-pinctrl
+ - rockchip,rk3188-pinctrl
+ - rockchip,rk3228-pinctrl
+ - rockchip,rk3288-pinctrl
+ - rockchip,rk3308-pinctrl
+ - rockchip,rk3328-pinctrl
+ - rockchip,rk3368-pinctrl
+ - rockchip,rk3399-pinctrl
+ - rockchip,rk3568-pinctrl
+
+ rockchip,grf:
+ description: |
+ phandle referencing a syscon providing the "general register files"
+ maxItems: 1
+
+ rockchip,pmu:
+ description: |
+ Optional. Phandle referencing a syscon providing the pmu registers
+ as some SoCs carry parts of the iomux controller registers there.
+ Required for at least rk3188 and rk3288. On the rk3368 this should
+ point to the PMUGRF syscon.
+ maxItems: 1
+
+ ranges: true
+
+patternProperties:
+ "^gpio[0-9]@[0-9a-f]":
+ type: object
+ description: gpio sub node
+
+ properties:
+ compatible:
+ enum:
+ - rockchip,gpio-bank
+ - rockchip,rk3188-gpio-bank0
+
+ reg:
+ maxItems: 2
+
+ interrupts:
+ description: Specifies the Rockchip summary IRQ
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description:
+ Specifies the PIN numbers and Flags, as defined in defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ clocks:
+ description: clock that drives this gpio bank
+ minItems: 1
+ maxItems: 2
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - clocks
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - rockchip,grf
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/rockchip.h>
+ pcfg_pull_default: pcfg_pull_default {
+ bias-pull-pin-default
+ };
+
+ pinctrl@20008000 {
+ compatible = "rockchip,rk3066a-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@20034000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20034000 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clk_gates8 9>;
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
+ <1 RK_PB1 1 &pcfg_pull_default>;
+ };
+ };
+ };
+
+ uart2: serial@20064000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x20064000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mux_uart2>;
+ pinctrl-0 = <&uart2_xfer>;
+ pinctrl-names = "default";
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ };
--
2.25.1


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