Messages in this thread | | | From | Namhyung Kim <> | Date | Wed, 14 Apr 2021 22:51:09 +0900 | Subject | Re: [PATCH V3 2/2] perf/x86: Reset the dirty counter to prevent the leak for an RDPMC task |
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Hi Kan,
On Wed, Apr 14, 2021 at 4:04 AM <kan.liang@linux.intel.com> wrote: > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index dd9f3c2..0d4a1a3 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -1585,6 +1585,8 @@ static void x86_pmu_del(struct perf_event *event, int flags) > if (cpuc->txn_flags & PERF_PMU_TXN_ADD) > goto do_del; > > + __set_bit(event->hw.idx, cpuc->dirty); > + > /* > * Not a TXN, therefore cleanup properly. > */ > @@ -2304,12 +2306,46 @@ static int x86_pmu_event_init(struct perf_event *event) > return err; > } > > +void x86_pmu_clear_dirty_counters(void) > +{ > + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > + int i; > + > + if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX)) > + return;
Maybe you can check it after clearing assigned counters.
Thanks, Namhyung
> + > + /* Don't need to clear the assigned counter. */ > + for (i = 0; i < cpuc->n_events; i++) > + __clear_bit(cpuc->assign[i], cpuc->dirty); > + > + for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) { > + /* Metrics and fake events don't have corresponding HW counters. */ > + if (is_metric_idx(i) || (i == INTEL_PMC_IDX_FIXED_VLBR)) > + continue; > + else if (i >= INTEL_PMC_IDX_FIXED) > + wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0); > + else > + wrmsrl(x86_pmu_event_addr(i), 0); > + } > + > + bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX); > +}
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